1. Field of the Invention
The present invention relates to a phase locked loop (to be referred to as a PLL, hereinafter) circuit, and more particularly to a PLL circuit which generates a clock signal to be supplied to an LSI (Large Scale Integrated Circuit).
2. Description of the Related Art
A PLL circuit of this type is conventionally used to generate a clock signal which is used in an LSI circuit. The structure of the PLL circuit which is used as a conventional clock signal frequency multiplying circuit is explained in "How to use PLL-IC" by Hata et al., (published from Akiba syuppan on Feb. 10, 1986, pp. 21 to 24 and pp. 75 to 78). In this reference, there is described a basic PLL circuit which is composed of a phase comparator, a loop filter and a voltage controlled oscillator, and a basic operation of the PLL circuit such as basic equations and a pull-in range in case of existing a delay time in a loop circuit.
FIG. 1 is a block diagram illustrating the structure of a conventional PLL circuit. As shown in FIG. 1, in the conventional PLL circuit, an output clock signal CLKOUT (terminal 133) is generated by a voltage controlled oscillator 45 and is frequency-divided by a frequency dividing circuit 46 to produce a synchronous clock signal SCLK (terminal 134). Then, the synchronous clock signal SCLK and an input clock signal CLKIN (terminal 130) are compared with each other by a phase comparator 43 to produce a phase difference signal U/D (terminal 131). A loop filter 44 removes a high frequency component from the phase difference signal U/D to produce a control signal CTR (terminal 132). The frequency of the output clock signal CLKOUT from the voltage controlled oscillator 45 is controlled based on the control signal CTR. As a result, the voltage controlled oscillator 45 is controlled in such a manner that the frequency difference between the input clock signal CLKIN and the synchronous clock signal SCLK and the phase difference between them are eliminated. Thus, the synchronous clock signal SCLK and the input clock signal CLKIN are made equal in frequency and phase.
Because the synchronous clock signal SCLK is obtained by dividing the output clock signal CLKOUT in frequency, the output clock signal CLKOUT has the frequency obtained by multiplying the frequency of the synchronous clock signal SCLK by a reciprocal of a division ratio of the frequency dividing circuit 46, e.g., 2 when the division ratio is 1/2. After all, the frequency of the output clock signal CLKOUT is obtained by multiplying the frequency of the input clock signal CLKIN by the reciprocal of the dividing ratio of frequency dividing circuit 46. By such a function, the PLL circuit can output the output clock signal which has the frequency N (N is a positive integer) times more than the frequency of the input clock signal.
In the structure of the above-mentioned conventional PLL circuit, there is a problem in that the reliability to the change of external parameters is low. In the conventional PLL circuit, the frequency of the output clock signal is controlled using a feedback control mechanism.
It is known that the feedback control mechanism becomes impossible to perform the control since the control signal diverges and oscillate when a loop gain is equal to or more than 1.
In the PLL circuit using a feedback control system, for example, there are a lot of control parameters such as gains of components such a phase comparator, a loop filter and a voltage controlled oscillator, and a phase delay value. Each of the parameters changes depending upon external parameters such as a power supply voltage, a temperature, a frequency. For this reason, in order to guarantee the control operation of the PLL circuit to the external parameters in an operation guarantee range, it is necessary to guarantee that all of combinations of the control parameters which are set by the external parameters in the operation guarantee range meet the condition for the feedback control.
Therefore, it is desirable that the operation guarantee range to the external parameter is wide. For this purpose, the following two methods could be considered,
1 it is to suppress the change of inner parameters depending upon the external parameters, and PA1 2 it is to take a wide margin of the control operation condition for the change of the inner parameters.
As a cause by which the loop gain in the feedback loop control mechanism is equal to or more than 1, there would be the case where the loop phase delay quantity becomes equal to or more than .pi. (180 degrees). In this case, because the loop which is originally a negative feed back becomes a positive feedback loop, the loop gain becomes equal to or more than 1 so that it becomes impossible to perform the control.
This loop phase delay is expressed as a summation of the phase delays of the respective components in the loop. In the feedback loop system which is used in a usual PLL circuit for the frequency multiplication, the phase delay quantity of the voltage controlled oscillator becomes .pi./2 theoretically, because it is an integration term of phase. Also, the phase delay quantity of the loop filter takes a value in a range of 0 to .pi./2 theoretically, because the loop filter is necessary to form a low-pass filter. However, it is desirable that the dumping constant value of the loop filter is larger, in order to suppress the change (jitter) of the time period of the output clock signal due to the change of the control signal in one control time period. As the result, the phase delay quantity of the loop filter needs to be set to a large value to some extent.
From the above-mentioned reasons, the loop phase delay in the usual PLL circuit for frequency multiplication becomes the value which is near .pi.. Therefore, the phase margin is small so that the reliability to the change of the external parameters becomes low.
The above-mentioned state will be described below more specifically. FIGS. 2A to 2E show operation waveforms in the conventional PLL circuit for frequency multiplication. The waveform 217 in FIG. 2A shows the waveform at a terminal 130 in FIG. 1, the waveform 218 shows the waveform at a terminal 134, the waveform 219 shows the waveform at a terminal 131, the waveform 220 shows the waveform at a terminal 132, and the waveform 221 shows the waveform at a terminal 133. It should be noted that the symbols of "P161" to "P165" in FIGS. 2A to 2E are phase errors between the input clock signal CLKIN and the synchronous clock signal SCLK.
In FIGS. 2A to 2E, the time period of the synchronous clock signal SCLK in the fifth time period of the input clock signal CLKIN shown in FIG. 2A as 5 is already shorter than the time period of the input clock signal CLKIN. In spite of this, the phase error shows that the synchronous clock signal SCLK is delayed in phase.
Therefore, it would be expected that the delay time control signal CTR for the voltage controlled oscillator becomes a further smaller value so that the time period of the synchronous clock signal SCLK will become shorter. This is because the phase error had accumulated because of the integration term in the voltage controlled oscillator 45 so that a right phase error could not be detected, i.e., the delay of the phase error detection occurs. Thus, when the delay of the phase error detection is large, divergence or oscillation is brought about in the phase control so that the phase synchronization cannot be accomplished. This is instability in the loop phase delay.
In this way, in the conventional PLL circuit, because the instability is brought about due to this loop phase delay, there is a problem in that the erroneous operation by the change of the external parameters is brought about.
In Japanese Laid Open Patent Application (JP-A-Showa 63-290019), a frequency synthesizer is described. In this reference, when a switch 56 is turned off to open a phase locked loop circuit, a reset signal is supplied to a variable frequency dividing circuit 52 to change the divided frequency into a first predetermined frequency in a first time period and into a second predetermined frequency for second predetermined time periods after the first time period. The phase difference is detected during the second predetermined time periods and the variable frequency dividing circuit 52 is set to output a third frequency. Then, the switch 56 is turned on to form a closed phase locked loop circuit. In this manner, the phase difference detecting operation is performed in the opened phase locked loop state.
In Japanese Laid Open Patent Application (JP-A-Heisei 7-86931) is described a frequency synthesizer which can shorten a pull in time in case of change of frequency. In this reference, the frequency synthesizer is composed of a basic oscillator 4, a voltage controlled oscillator 1, a programmable counter 2, a charge pump type phase comparator 6, a loop filter 7 and an adder 8. In order to change a frequency, a frequency setting of the programmable counter 2 and a voltage setting of a reference voltage generating circuit 9 are changed. Also, a reset signal synchronous with a signal from the basic oscillator 4 in phase is supplied to the programmable counter 2. At the same time, a switching circuit 5 connected to inputs of the phase comparator 6 is operated. Thus, it is made possible to perform a fast pull-in operation even if an output frequency of the voltage controlled oscillator 1 is changed due to an ambient temperature.
As described above, in the conventional PLL circuit, the instability due to the external parameters is not yet sufficiently eliminated.